The present invention relates generally to fabrication of semiconductor devices, and more particularly to a method for forming a resist protect layer that has an improved etch selectivity.
A silicide layer is usually formed atop silicon structures, such as polysilicon gates, source/drain regions and local interconnects, in a semiconductor device in order to reduce a sheet resistance. In the process of forming the silicide layer, a resist protect layer is used to cover some parts of the silicon structures and expose some predetermined areas. A metal layer is blanketly deposited over the resist protect layer and exposed areas. A thermal treatment is then performed to facilitate a chemical reaction where the metal layer is in contact with the silicon structures to form the silicide layer. Because the resist protect layer shields a part of the semiconductor device from the metal layer, no silicide layer would be formed on the covered portions in the course of the thermal treatment. The unreacted part of the metal layer is then stripped, leaving the silicide layer on desired areas.
FIG. 1A illustrates a cross-sectional view of a semiconductor device 10 in a conventional fabrication process. A Shallow Trench Isolation (STI) 101 defines a first area 102 and second area 103 on a semiconductor substrate 104. In the first area 102, a gate oxide layer 105 separates a gate electrode 106 from the semiconductor substrate 104. Spacer liners 107 and spacers 108 are formed on the side walls of the gate electrode 106. Source/drain regions 109 are formed adjacent to the spacers 108 in the semiconductor substrate 104. In the second area 103, a resistor 110 and an insulator layer 111 is formed on the semiconductor substrate 104. A resist protect oxide layer 112 is blanketly deposited over the source/drain regions 109, spacers 108, spacer liners 107, gate electrode 106, STI 101 and resistor 110. A photoresist mask 113 is formed on the resist protect oxide layer 112 in such a way to cover the second area 103 and expose the first area 102.
In the semiconductor device 10, only the gate electrode 106 and source/drain regions 109 require a formation of a silicide layer, so that it is desirable to remove the resist protect oxide layer 112 from the first area 102, while keeping it in the second area 110. Accordingly, a photoresist mask 113 is so defined to shield the second area 103 and expose the first area 102. A step of wet etching using an HF solution is performed to remove the exposed part of the resist protect oxide layer 112. Then the photoresist mask 113 is stripped off to leave the semiconductor structure 10, as shown in FIG. 1B.
The conventional process of forming the resist protect oxide layer 112 has a problem of undercutting the spacer liner 107, and damaging the STI 101. Because the spacer liners 107 and STI 101 are made of oxide materials, their etch rate would be very close to the resist protect oxide layer 112. In a 100:1 HF solution, the etch rate for the resist protect oxide layer 112 is about 70 Angstroms per minute, and the etch rates for the spacer liner 107 and the STI 101 are about 200 Angstroms per minute and 50 Angstroms per minute, respectively. Thus, using the HF solution to etch the resist protect oxide layer 112 is very unselective with respect to the spacer liners 107 and the STI 101. The undercut 114 and divot 115 are often formed after the wet etching process. This would degrade device performance, and cause junction leakage associated with a subsequently formed silicide layer.
Another problem of the conventional process is that the resist protect layer 112 left in the second area 103 is still vulnerable to etching by an HF solution in a subsequent pre-metal dip process. In a conventional salicide (Self-Aligned Silicide) process, the semiconductor structure 10 would be dipped in an HF solution to remove oxide residue and other contaminants before a metal layer is formed thereon. This may damage the remaining resist protect oxide layer 112, and cause an undesired silicide formation on the resistor 110.
FIG. 2 illustrates a resist protect layer formed on a semiconductor device 20, according to a conventional process. This process uses a stacked resist protect layer 201, which includes an oxide layer 202 and a nitride layer 203, blanketly deposited over a gate 204 and resistor 205 on a semiconductor substrate 206. A photoresist mask 207 covers the part of the stacked resist protect layer 201 above the resistor 205 and exposes the left part above the gate 204. A dry etching is performed to remove the part of the nitride layer 203 uncovered by the photoresist mask 207. Then, a wet etching using an HF solution is performed to remove the part of the oxide layer 205 uncovered by the photoresist layer 207. The process takes advantage of the nitride layer 203 to reduce the thickness of the oxide layer 202, so that the wet etching can be performed in a relatively short time. This reduces an undesirable impact, such as a formation of divot, that the HF solution may have on an STI 208.
While the process reduces the time required for the wet etching by using a thin oxide layer 202, it has some drawbacks. Due to the geometry of the semiconductor structure 20, the dry etching may not remove the uncovered nitride layer 203 completely. This results in a residual nitride layer 209 at the bottom corner of spacers 210. Furthermore, the dry etching usually involves gaseous chemicals and high energy ions. Given the thinness of the oxide layer 202, it is difficult to protect the semiconductor substrate 206 from damages by the chemicals and ions. In addition, the process requires not only two deposition steps for forming the nitride layer 203 and the oxide layer 202, but also a dry etching step and wet etching step for partially removing the same. This complicates the fabrication of semiconductor devices and results in a low throughput and high cost.
What is needed is a simple method for forming a resist protect layer on a semiconductor device without causing substantially structural damage and residuals.